Classic Computer Magazine Archive START VOL. 3 NO. 9 / APRIL 1989


Our research into the netherworld of Reduced Instruction Set Computers managed to unearth things both mundane and strange. Perhaps most intriguing was this unsigned document, a "lead'' from an anonymous FAXer--obviously wary of giving a company name. We offer it to you here in its entirety--a sign of things to come?

A recent trend in computer architecture, especially for microprocessor implementations, is the Reduced Instruction Set Computer (RISC). RlSCs are characterized by a small number of simple instructions that typically execute in a single machine cycle. By combining this concept with a large, high-speed register file, RISC proponents have produced many machines that outperform their complex (CISC) brethren.

The SISC extends the concept of RISC architecture to the fullest degree. Basically, the SISC implements a single, yet extremely powerful, instruction. The result is a flexible, low-cost processor that outperforms many designs containing tens of thousands more transistors. Since there is only a single instruction, an order-of-magnitude reduction in processor complexity is achieved. The SISC operates with no instruction pipeline and no instruction cache. These elements, which add cost and complexity to other processors, are entirely unnecessary on the SISC: The "next" instruction is always the same as the previous one. There is no need to fetch an opcode and no need to decode one. Every cycle is an execution cycle on the SISC. And with no opcodes to fetch, there is also no need for an instruction register or program counter, thus further simplifying the design.

The elegance of the SISC processor is embedded in its single multipurpose instruction: INC A. This instruction, the only one available on the SISC, adds one to the contents of the accumulator and stores the result in the accumulator. The value of this approach becomes apparent when one considers that both operands are implied by the instruction itself, as is the destination. Consequently, no memory cycle is required. Ever. This leads to the surprising result that the SISC can operate with no memory at all, a conclusion we have verified experimentally. The savings in memory management circuitry, RAM control, and memory devices themselves are substantial. It may be the second-biggest advantage SISC holds over other, more traditional designs.

By far the first advantage is the elimination of software. Most new processors suffer in the marketplace because of an initial lack of programming tools and utilities. But the SISC, with only one instruction, requires no software. INC A, INC A, INC A. That's all there is to it.

A traditionalist may question the value of a processor with no memory, no software, and only one-instruction. But we have verified, at least statistically, that the SISC can produce any result that any other computer can produce. And usually it does it faster.

In one test of the SISC's capabilities, an array of SISC processors was used to drive a 1,024 X 1,024 raster graphics display. Each SISC was wired to a single pixel; the result held in each SlSC's accumulator selected a pixel's color and luminance parameters. When the SISCs were fired up, the display produced a dazzling array of images: a frowning Mona Lisa, a picture of what Gorbachev is doing right now, and the complete set of blueprints for the Stealth bomber (along with several decoys). So in addition to possible applications in the arts, the SISC may have national security applications. Other, more mundane applications include an odometer for automobiles, and tracking the national debt.

The current generation of SISC processors is fabricated of germanium PNP transistors in TO-5 cans. Samples are available, now, with volume shipments beginning April 1.

Copyright (c) 1988 by CMP Publications, Inc., 600 Community Drive, Manhasset, NY 11030. Reprinted with permission from Computer Systems News.