Expanding KIM-Style 6502 Single Board Computers
The Modified KIM Bus
Part 3 of 3
This leads us to a definition of the "Unbuffered Modified KIM Bus". KIM is part of the name since the bus is essentially what a KIM-1 single board computer presents on its expansion connector. "Modified" is part of the name because not all of the 44 signals on the expansion connector are actually part of the bus. Those signals that are part of the bus are common to the SYM and AIM computers as well as the KIM and thus any of these machines may be plugged into the bus without modification.
Figure 6 gives a signal listing for the bus. Signals marked with an * do not connect to the processor but do connect to all of the other boards in the system. Most of these have different specialized functions on the different processors anyway and are not generally useful in a bus oriented system. Note that RDY is one of the signals that is not bussed. All modern memories are quite fast enough to operate without wait states in 6502 systems and besides, the 6502 will not wait during write cycles anyway. The lines marked (Reserved) are intended for future uses such as memory bank switching signals, etc.
Note that although RAM R/W is listed as a signal (should go low during phase 2 of Write cycles), it should not be used by a bus interface board for general application. The reason is that an AIM-65 printed circuit error makes it go low during read cycles rather than write cycles like it should. In any case, one should be able to design any kind of bus interface board using just A0 - A15, D0 - D7, R/W, PHASE 2, interrupt, and power voltages. The additional lines are really just convenience signals.
Two of the signals are important only in KIM systems. DECODE ENABLE must go low whenever addresses between 0000 and 1FFF are on the bus in order to activate KIM's on-board memory. VECTOR FETCH must go low whenever addresses between FFFA and FFFF are on the bus in order for the reset/interrupt vectors stored in the KIM monitor ROM's to be active. Although it is probably best for the motherboard to generate these two signals, many expansion boards generate them anyway so that the bus motherboard can be omitted altogether in systems with just one expansion board.
Note that direct memory access is not supported by the Modified KIM Bus because the address lines from the 6502 cannot be disabled. An approach to DMA in those interfaces that need it, such as video displays and disk controllers, is to provide two-port memory on the interface board itself. The big advantage then is that DMA to or from the on-board memory can then proceed at very high speed without slowing the processor at all. A conventional DMA system, such as on S-100 systems, would stop the processor cold at data rates beyond a couple of hundred thousand bytes per second.
Although +5 volts regulated is available on the bus, it is often preferable to use unregulated +8 and an on-board regulator to provide +5 to the logic circuitry of expansion boards. Similarly, +16 unregulated is available for generating +12 power needed by many memory chips. When negative voltages are needed such as for EPROM's or analog circuitry, they may be easily generated from the positive unregulated voltages with a charge-pump circuit and then regulated with IC regulators. The primary advantages of on-board regulation are a smaller and less expensive central power supply and clean, well regulated power on the expansion board itself. The potential problem of additional heat dissipation on the expansion boards is nullified by the very low power consumption of modern LS IC's.
|E-3||PHASE 1||PHASE 1||PHASE 1||(reserved)|
|E-8||DATA BUS 7||DATA BUS 7||DATA BUS 7||DATA BUS 7|
|E-9||DATA BUS 6||DATA BUS 6||DATA BUS 6||DATA BUS 6|
|E-10||DATA BUS 5||DATA BUS 5||DATA BUS 5||DATA BUS 5|
|E-11||DATA BUS 4||DATA BUS 4||DATA BUS 4||DATA BUS 4|
|E-12||DATA BUS 3||DATA BUS 3||DATA BUS 3||DATA BUS 3|
|E-13||DATA BUS 2||DATA BUS 2||DATA BUS 2||DATA BUS 2|
|E-14||DATA BUS 1||DATA BUS 1||DATA BUS 1||DATA BUS 1|
|E-15||DATA BUS 0||DATA BUS 0||DATA BUS 0||DATA BUS 0|
|E-16||K6||30||-12 VOLTS REG.||* (reserved)|
|E-17||SINGLE STEP OUT||DB OUT||+ 12 VOLTS REG.||* (reserved)|
|E-18||(N.C.)||POWER ON RESET||* + 7.5 UNREG|
|E-19||(N.C.)||(N.C.)||* VECTOR FETCH|
|E-20||(N.C.)||(N.C.)||* DECODE ENABLE|
|E-21||+5 VOLT REG.||+5 VOLT REG.||+5 VOLT REG.||+5 VOLT REG.|
|E-A||ADDR BUS 0||ADDR BUS 0||ADDR BUS 0||ADDR BUS 0|
|E-B||ADDR BUS 1||ADDR BUS 1||ADDR BUS 1||ADDR BUS 1|
|E-C||ADDR BUS 2||ADDR BUS 2||ADDR BUS 2||ADDR BUS 2|
|E-D||ADDR BUS 3||ADDR BUS 3||ADDR BUS 3||ADDR BUS 3|
|E-E||ADDR BUS 4||ADDR BUS 4||ADDR BUS 4||ADDR BUS 4|
|E-F||ADDR BUS 5||ADDR BUS 5||ADDR BUS 5||ADDR BUS 5|
|E-H||ADDR BUS 6||ADDR BUS 6||ADDR BUS 6||ADDR BUS 6|
|E-J||ADDR BUS 7||ADDR BUS 7||ADDR BUS 7||ADDR BUS 7|
|E-K||ADDR BUS 8||ADDR BUS 8||ADDR BUS 8||ADDR BUS 8|
|E-L||ADDR BUS 9||ADDR BUS 9||ADDR BUS 9||ADDR BUS 9|
|E-M||ADDR BUS 10||ADDR BUS 10||ADDR BUS 10||ADDR BUS 10|
|E-N||ADDR BUS 11||ADDR BUS 11||ADDR BUS 11||ADDR BUS 11|
|E-P||ADDR BUS 12||ADDR BUS 12||ADDR BUS 12||ADDR BUS 12|
|E-R||ADDR BUS 13||ADDR BUS 13||ADDR BUS 13||ADDR BUS 13|
|E-S||ADDR BUS 14||ADDR BUS 14||ADDR BUS 14||ADDR BUS 14|
|E-T||ADDR BUS 15||ADDR BUS 15||ADDR BUS 15||ADDR BUS 15|
|E-U||PHASE 2||PHASE 2||PHASE 2||PHASE 2|
|E-X||PLL TEST||AUDIO TEST||AUDIO TEST||* + 16 VOLT UNREG.|
|# These signals are not bussed to the CPU slot.|
|# Signal generated Is different from KIM-1 and SYM-1.|