130XE: HOW ATARI'S
NEW 8-BIT DOES IT

Just before publication deadline, Atari released first specifications for their new 130XE computer.  We wasted no time in passing along the most important points to technical-minded readers.-ANTIC ED.

The l30XE provides its owner with 128K of system RAM. Since it is an 8-bit machine and therefore incapable of addressing more than 64K of memory, the extra 64K is accessed through selective bank switching.
   Atari states that any software developed for the 130XE which does not use the extra RAM will be 100% compatible with their new 64K 8-bit 65XE computer. And of course the 65XE is being billed as 100% compatible with the 800XL model it replaces.
   The announced differences between the l30XE and the 65XE are:

1. RAM capacity and organization.

2. Altered usage of the 6520 PLA (Parallel Interface Adaptor).

3. Increased power supply requirements. (1.2 amps at 5 VDC for the 130XE)

4. Enhanced Cartridge Interface.

Figure 1

1. Compatibility mode:

VBE CBE BA1 BA0 CPU Access Video Access 1 1 X X Main $4000-$7FFF Main $4000-$7FFF

2. CPU Extended RAM mode:

VBE CBE BA1 BA0 CPU Access Video Access 1 0 0 0 Exp $0000-$3FFF Main $4000-$7FFF 1 0 0 1 Exp $4000-$7FFF Main $4000-$7FFF 1 0 1 0 Exp $8000-$BFFF Main $4000-$7FFF 1 0 1 1 Exp $C000-$FFFF Main $4000-$7FFF

3. Video Extended RAM mode:

VBE CBE BA1 BA0 CPU Access Video Access 0 1 0 0 Main $4000-$3FFF Exp $0000-$3FFF 0 1 0 1 Main $4000-$7FFF Exp $4000-$7FFF 0 1 1 0 Main $4000-$7FFF Exp $8000-$BFFF 0 1 1 1 Main $4000-$7FFF Exp $C000-$FFFF

4. Extended RAM mode:

VBE CBE BA1 BA0 CPU Access Video Access 0 0 0 0 Exp $0000-$3FFF Exp $0000-$3FFF 0 0 0 1 Exp $4000-$7FFF Exp $4000-$7FFF 0 0 1 0 Exp $8000-$BFFF Exp $8000-$BFFF 0 0 1 1 Exp $C000-$FFFF Exp $C000-$FFFF

   The "Enhanced Cartridge Interface" (ECI) is the new parallel bus which will only be available on the 130XE. It's designed as an extension to the cartridge slot and Atari claims it "provides equivalent architectural functionality" to the PBI on the XL line. Whether it provides physical equivalence and, if not, whether hardware manufacturers will want to make double plugs for compatible hardware remains to be seen.
   See Figure 2 for a chart of ECI signals. No pin numbers were available at press time.

TWO BANKS
The two 64K banks of memory in the 130XE are called the "main bank" and the "secondary bank." They are identical in layout and control capacity and may be accessed by either the 6502 or ANTIC microchips in various combinations, through manipulation of four previously unused flag bits in the 6520 PLA registers (beginning at $D300).
   The first flag bit is the Video (ANTIC) Bank Enable which, when set to zero, enables video data fetches from the extended RAM. The second bit is the CPU Bank Enable. This allows CPU access of the secondary bank.
   The secondary bank is approached through a 16K "access window" at locations $4000-$7FFF At any one time, only one 16K "page" is accessible through this window. The final two new PLA bits are used to specify the chosen page address for the extra 64K bank.
   These four bits, along with the ability of both the CPU as well as ANTIC to access the new RAM, provide some interesting combinations. There are four distinct modes of operation:

1. Compatibility mode.

2. CPU extended RAM.

3. Video extended RAM.

4. Extended RAM mode.

   In CPU extended mode, only the CPU has access to the secondary bank, ANTIC sees the main bank. Keep in mind that any access to the extended RAM is only through the access window at $4000-$7FFF. In this mode, you could place your display lists and screen information in main memory and use extended RAM for program and data storage. No synchronization of bank addressing with display activity is required on the part of the programmer!
   The Video extended RAM mode is essentially the reverse of the above. The secondary bank is accessed by ANTIC while it remains invisible to the CPU.
   In Compatibility mode, both ANTIC and the CPU see the main bank. In Extended RAM mode, they both see the secondary bank. Figure 1 shows how setting the PLA bits affects the CPU and ANTIC access for the various modes.
   So what are you going to do with all this new stuff? A practical, applications-minded programmer could create quite a database program with this but as for me, I see an Eastern Front with an eight-way scrolling map that just won't quit!

Figure 2

ENHANCED CARTRIDGE INTERFACE
CONNECTOR

---- | | | | present 30 pin cart conn | | | ---- | | | | 14 pin extension | | | | | -----

ECI Conn A0-A12 D0-D7 R/W* PH12 +5V GRD S4 S5 RD4 RD5 CCTL A13-A15 REF MPD RESET* IRQ AUDIO IN I/O1* HALT* Extsel Reserved GND +5V

Description 1st 13 Address Lines. System data bus. Processor read/write. System Clock. DC Power. Ground. Chip select $8000-9FFF. Chip select $A000-BFFF. ROM present. ROM present. ROM bank control select. Upper 3 Address Lines. Present cycle is a refresh. Math pack disable. System reset. Interrupt request. External audio input. Chip select at D1XX. ANTIC halt* signal. External memory assertion. Reserved signal line. Second ground. Second power.